Computer monitor device

ABSTRACT

A microcomputer is not stopped to be monitored even in a state in which a wrong standby signal is detected.  
     A watchdog circuit  34  outputs a starting signal to a microcomputer  30.  An output signal Q of a determination circuit  36  is reset by this starting signal. If the determination circuit does not detect a standby signal st when a clock signal CK is input from the started microcomputer, the output signal is set. However, if the determination circuit detects the standby signal st, the output signal is held in a reset state. Even if the standby signal st is input, because an AND circuit  38  does not output a standby signal ST due to the reset of the output signal Q, the watchdog circuit is prevented from entering a standby mode by the standby signal st.

TECHNICAL FIELD

[0001] The present invention relates to a computer monitoring devicewhich monitors whether a computer provided at a power window system of avehicle or the like operates normally.

TECHNICAL BACKGROUND

[0002] Conventionally, in a system using a microcomputer in which abattery is a power supply, when the microcomputer is not used, themicrocomputer enters a standby mode and the execution of a program isstopped in order to reduce electricity consumption of the battery.Further, a microcomputer monitoring circuit (watchdog circuit) isprovided in the system using the microcomputer. The microcomputermonitoring circuit monitors a state of the microcomputer by the outputof a predetermined signal (e.g., a signal which is generated on thebasis of a clock signal and will be hereinafter referred to as “clocksignal”) from the microcomputer. When the clock signal is not detected,the microcomputer monitoring circuit determines that the state of themicrocomputer is not normal and outputs a signal which restarts themicrocomputer (hereinafter, “restarting signal”).

[0003] On the other hand, because the microcomputer stops the output ofthe above-described clock signal by entering the standby mode, themicrocomputer monitoring circuit outputs the restarting signal. As aresult, the microcomputer which is supposed to enter the standby mode isrestarted.

[0004] In order to prevent the restarting of the microcomputer which issupposed to enter the standby mode, when the microcomputer monitoringcircuit detects a signal which is output when the microcomputer entersthe standby mode (hereinafter, “standby signal”), the microcomputermonitoring circuit also enters the standby mode. Namely, when thestandby signal is detected, the microcomputer monitoring circuit entersthe standby mode and stops the monitoring function of the microcomputer.

[0005] An example of a system which includes the microcomputer and themicrocomputer monitoring circuit is a power window system of a vehicle.In this power window system, a microcomputer controls a relay or thelike and operates a motor for raising and lowering a door glass inaccordance with a switch operation. At this time, a microcomputermonitoring circuit monitors an operating state of the microcomputer inorder to prevent the control of the motor from being disabled due torunaway or the like of the microcomputer. When it is determined that themicrocomputer does not operate normally, a restarting signal is outputto the microcomputer.

[0006] On the other hand, the power window system includes amicrocomputer control system and an SW control system (direct control bya switch) so as to control the motor in accordance with the switchoperation. The motor is usually controlled by the microcomputer controlsystem. When the microcomputer enters the standby mode or it isdetermined by the operating state of the microcomputer monitoringcircuit that the operation of the microcomputer fails, the motor iscontrolled by the SW control system. In this way, the motor can becontrolled even if the microcomputer does not operate normally.

[0007] By the way, when a microcomputer port or an input terminal of themicrocomputer monitoring circuit fails, the standby signal may be inputto the microcomputer monitoring circuit by mistake. In this case, evenwhen the microcomputer becomes abnormal and the restarting signal isoutput, since the microcomputer monitoring circuit detects the standbysignal, the microcomputer monitoring circuit enters the standby mode andstops monitoring of the microcomputer which is a fundamental function.

[0008] In order to prevent this, a microcomputer monitoring circuit hasbeen proposed which, when a restarting signal is output, does not entera standby mode even if a standby signal is detected. This microcomputermonitoring circuit enters the standby mode when the microcomputermonitoring circuit detects the signal entering the standby mode from thetime in which a predetermined signal output from the microcomputer isnot detected to the time in which a signal restarting the microcomputeris output. As a result, when the microcomputer becomes abnormal and thepredetermined signal is not detected, even if the signal entering thestandby mode is detected, the microcomputer monitoring circuit canoutput the signal which urges the restarting of the microcomputerwithout stopping the monitoring function.

[0009] However, in this computer monitoring device (microcomputermonitoring circuit), when the microcomputer is restarted or the like ina state in which a wrong standby signal is detected and the devicedetects a predetermined signal which is output from the microcomputer atthe time of normal operation thereof, it is determined that themicrocomputer operates normally. At this time, the computer monitoringdevice enters the standby mode since the standby signal is detected.Thus, there is a drawback in that the monitoring of the microcomputer isstopped.

[0010] The present invention was developed in light of the abovecircumstances, and the object thereof is to provide a computermonitoring device which does not enter a standby mode even if a standbysignal is input by mistake.

DISCLOSURE OF THE INVENTION

[0011] In order to solve the above-described problems, the presentinvention comprising: starting means which outputs a starting signalbefore starting a computer, the starting means outputting a startingsignal to the computer when a first signal, which is output from thestarted computer in a predetermined cycle, is stopped for apredetermined period of time; start stopping means which stops anoperation of the starting means when a second signal, which is outputfrom the computer with a predetermined timing, is input; start operationdetermination means which outputs a third signal, which urges stoppingof an operation of the start stopping means, due to inputting of thestarting signal, the start operation determination means stoppingoutputting of the third signal by the first signal which is output fromthe computer only when the second signal is not detected; and operationmonitoring means which stops outputting of the input second signal tothe start stopping means when the start operation determination meansoutputs the third signal.

[0012] In accordance with the present invention, the starting meansoutputs the starting signal after a predetermined period of time haspassed since the first signal, which is output from the computer in apredetermined cycle, is not input. When the second signal, which isoutput from the computer at the time of entering the standby mode, isdetected, the start stopping means stops the operation of the startingmeans. As a result, since the computer outputs the second signal whenentering the standby mode, even if the computer which enters the standbymode stops the output of the first signal, the computer is not startedby the starting signal.

[0013] On the other hand, the start operation determination meansoutputs the third signal due to the input of the starting signal andstops the output of the third signal when the first signal is detectedbefore the second signal is detected. Further, the operation monitoringmeans outputs the second signal to the start stopping means due to thedetection of the second signal and, when the third signal is detected,the output of the second signal to the start stopping means is stopped.

[0014] In this way, the starting means can be operated on the basis ofthe first signal and outputs the starting signal if the computer stopsthe output of the first signal. Accordingly, when the computer isstarted and the second signal is input by mistake, the computer can bemonitored due to the output of the third signal. When the first signalis not input, the starting signal for operating the computer normallycan be output.

[0015] Further, in the present invention, when the start operationdetermination means detects the first signal in a state in which thesecond signal is not detected, the output of the third signal isstopped. Consequently, the state in which the microcomputer operates ornot can be monitored by the output of the start operation determinationmeans and the operation monitoring means.

[0016] Namely, when the computer operates normally, it can be determinedthat the second and the third signals are not detected. Further, whenonly the second signal output from the operation monitoring means isdetected, it can be determined that the computer enters the standbymode. When the third signal output from the start operationdetermination means is detected, it can be determined that the computeris restarted.

[0017] Therefore, when the present invention is applied, for example, tomonitor the computer of the power window system, only when the secondsignal or the third signal is not detected, it can be determined thatthe computer operates normally. Thus, switching between themicrocomputer control system and the SW control system may be effectedon the basis of this result of determination.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic perspective view which shows the internalstructure of a vehicle operator's seat side door of a presentembodiment.

[0019]FIG. 2 is a block diagram of a power window system relating to thepresent embodiment.

[0020]FIG. 3(A) is a logical circuit diagram which shows an example of adetermination circuit and FIGS. 3(B) through 3(D) are timing charts onthe basis of the logical circuit diagram shown in FIG. 3(A).

[0021]FIG. 4 is a block diagram which shows an example of a relaycontrol circuit.

[0022]FIG. 5 is a timing chart which shows an operation of the relaycontrol circuit.

[0023] FIGS. 6(A) through 6(D) are timing charts which show operationsof a control circuit.

EMBODIMENTS

[0024]FIG. 1 shows the internal structure of a vehicle operator's seatside door 12. The inner portion of the vehicle operator's seat side door12 includes a motor 14 used in a power window system 10 which is appliedto a present embodiment. A window regulator portion 16 is connected tothis motor 14. In the present embodiment, the window regulator portion16 is a so-called wire type and an intermediate portion of a wire (notshown) is wound around a rotational plate 14A which is attached to adrive shaft of the motor 14. Each of the end portions of this wire isconnected to a holding channel 20 which supports the lower end portionof a door glass 18, and further, the holding channel 20 is attached to amain guide 22 so as to be able to move in the vertical directions.

[0025] In this way, when the motor 14 rotates in the forward and reversedirections, the holding channel 20 moves along the main guide 22 and thedoor glass 18 moves in the vertical directions (rises and lowers) alongglass guides 24. The window regulator portion 16 is not limited to thewire type and may be an X-arm type, a so-called motor-driven type inwhich a motor itself moves along a rack, or the like.

[0026] When the door glass 18 is raised by the driving of the motor 14,the peripheral end portion of the door glass 18 fits with a weatherstrip (not shown) which is formed of a rubber and is provided within aframe 12A of the door 12, and an opening of the door frame 12A isclosed. Further, when the door glass 18 is lowered by the driving of themotor 14, the opening of the frame 12A which has been closed is opened.

[0027]FIG. 2 shows a control system which drives the motor 14 of thepower window system 10. This control system comprises a microcomputer 30and a control circuit 32. The microcomputer 30 is formed so that anunillustrated CPU, ROM, RAM, and various types of interfaces areconnected by buses. The control circuit 32 includes a watchdog circuit34, a determination circuit 36, an AND circuit 38, and a relay controlcircuit 40. A microcomputer monitoring device 28, to which the presentinvention is applied, is formed by the watchdog circuit 34, thedetermination circuit 36, and the AND circuit 38.

[0028] An UP switch SW_(U) for raising the door glass 18 and a DOWNswitch SW_(D) for lowering the door glass 18 are connected to themicrocomputer 30 and the relay control circuit 40.

[0029] When the microcomputer 30 detects that the UP switch SW_(U) isturned on, an UP signal is output to the relay control circuit 40 via anexclusive line 42A. Further, when the microcomputer 30 detects that theDOWN switch SW_(D) is turned on, a DOWN signal is output to the relaycontrol circuit 40 via an exclusive line 42B. When the UP switch SW_(U)is turned on, an SWUP signal is input to the relay control circuit 40via a switch wiring 44A. When the DOWN switch SW_(D) is turned on, anSWDOWN signal is input to the relay control circuit 40 via a switchwiring 44B.

[0030] In an ordinary operating state, the microcomputer 30 outputs asignal having predetermined cycles such as a signal, which has beengenerated by synchronizing with, for example, a clock signal or thelike, to the control circuit 32 as a first signal (hereinafter, “clocksignal CK”). This clock signal CK is input to the watchdog circuit 34and the determination circuit 36 of the control circuit 32. The watchdogcircuit 34 comprises start stopping means and starting means. The watchdog circuit 34 includes, for example, a timer circuit which isreset/started by the input of the clock signal CK and outputs a startingsignal (reset signal RS) when a measuring time of this timer circuitreaches a predetermined time and the time is up. This reset signal RS isinput from the control circuit 32 to the microcomputer 30, and themicrocomputer 30 is started or restarted by the input of the resetsignal RS.

[0031] Namely, when the clock signal CK is input to the watchdog circuit34 at predetermined cycles, the watchdog circuit 34 does not output thereset signal RS. When the clock signal CK is not input, the watchdogcircuit 34 outputs the reset signal RS and restarts the microcomputer30. The reset signal RS can be switched from an H-level to an L-level.

[0032] On the other hand, the microcomputer 30 outputs a standby signalst to the control circuit 32 as a second signal. This standby signal stis input to the determination circuit 36 and the AND circuit 38, andfurther, a signal which is in accordance with the standby signal st(standby signal ST) is input from the AND circuit 38 to the watchdogcircuit 34.

[0033] When the microcomputer 30 enters the standby mode for savingelectricity or the like, the microcomputer 30 outputs the standby signalst. When the standby signal ST in accordance with the standby signal stis input from the AND circuit 38, the watchdog circuit 34 enters thestandby mode.

[0034] When the watchdog circuit 34 enters the standby mode, theoperation of the timer is stopped. In this way, even if themicrocomputer 30 enters the standby mode and the output of the clocksignal CK is stopped, the watchdog circuit 34 does not output the resetsignal RS. Namely, when the standby signal ST in accordance with thestandby signal st which is output from the microcomputer 30 is input,the watchdog circuit 34 enters the standby mode and stops monitoring ofthe microcomputer 30. When the standby signal ST in accordance with thestandby signal st is stopped, the watchdog circuit 34 which has enteredthe standby mode resumes monitoring of the microcomputer 30.

[0035] As shown in FIG. 3(A), the determination circuit 36 which isprovided as start operation determination means of the present inventioncomprises an inverter circuit 46, an AND circuit 47, and an RS flip-flopcircuit (RS-FF, hereinafter “FF circuit 48”). The standby signal st isinput to the AND circuit 47 via the inverter circuit 46 and the clocksignal CK is input to the AND circuit 47. In this way, the AND circuit47 outputs a set signal S to the FF circuit 48 in accordance with theclock signal CK and the standby signal st which is input via theinverter circuit 46.

[0036] Further, the reset signal RS output from the watchdog circuit 34is input to the FF circuit 48 as a reset signal R. The FF circuit 48resets an output signal Q due to the input of the reset signal R. In thepresent embodiment, the reset output signal Q is a third signal.

[0037] Namely, as shown in FIG. 3(B), in the determination circuit 36,the determination signal Q is held at an H-level by the input of the setsignal S. Further, when the reset signal R is input, the determinationsignal Q is reset and held until the next set signal S is input, and isoutput as a third signal. Moreover, as shown in FIG. 3(C), in thedetermination circuit 36, when the reset signal R is input again, theoutput signal Q of the FF circuit 48 is reset.

[0038] On the other hand, as shown by a double-dashed chain line in FIG.3(C), in the determination circuit 36, even if the clock signal CK isinput, the set signal S is not output by the input of the standby signalst. At this time, the output signal Q is reset by the input of the resetsignal R. When, for example, an unillustrated ignition switch of thevehicle is turned on and a power supply voltage Vcc is applied, thewatchdog circuit 34 outputs the reset signal RS and starts themicrocomputer 30.

[0039] Consequently, as shown in FIG. 3(D), when supply of the powersupply voltage Vcc is started, the determination circuit 36 is reset bythe reset signal R output from the watchdog circuit 34. However, whenthe standby signal st is detected at this time, the determinationcircuit 36 does not output the set signal S even if the clock signal CKis input. In this way, the output signal Q of the determination circuit36 is held in a reset state.

[0040] On the other hand, as shown in FIG. 2, the output signal Q of thedetermination circuit 36 and the standby signal st output from themicrocomputer 30 are input to the AND circuit 38 which is provided asoperation monitoring means of the present invention. When themicrocomputer 30 outputs the standby signal st, this AND circuit 38outputs the standby signal st as the standby signal ST to the watchdogcircuit 34 and the relay control circuit 40 in accordance with theoutput signal Q of the determination circuit 36.

[0041]FIG. 3 shows an example of the relay control circuit 40. Thisrelay control circuit 40 is provided with four AND circuits 50, 52, 54,and 56. The UP signal output from the microcomputer 40 is input to oneinput terminal of the AND circuit 50, the SWUP signal of the UP switchSW_(U) is input to one input terminal of the AND circuit 52, the DOWNsignal output from the microcomputer 40 is input to one input terminalof the AND circuit 54, and the SWDOWN signal of the DOWN switch SW_(D)is input to one input terminal of the AND circuit 56.

[0042] Further, as shown in FIG. 2, the standby signal ST which isoutput from the AND circuit 38 and the output signal Q which is outputfrom the determination circuit 36 are input to the relay control circuit40.

[0043] As shown in FIG. 4, the standby signal ST and the output signal Qare input to an OR circuit 74. The output signal Q is input to the ORcircuit 74 via an inverter circuit 76 as an inverted signal Q*.

[0044] A signal which is output from the OR circuit 74 is input to theother input terminals of the AND circuits 52 and 56, and further, theoutput signal of the OR circuit 74 is inverted by an inverter circuit 56and input to the AND circuits 50 and 54.

[0045] Output terminals of the AND circuits 50 and 52 are connected toinput terminals of an OR circuit 60, and an output terminal of this ORcircuit 60 is connected to the base of a transistor 62. Moreover, outputterminals of the AND circuits 54 and 56 are connected to input terminalsof an OR circuit 64, and an output terminal of this OR circuit 64 isconnected to the base of a transistor 66.

[0046] In this way, as shown in FIG. 5, when the standby signal ST orthe signal Q* inverted from the output signal Q is held at an L-level,the signals, which are output from the OR circuits 60 and 64 by theoutput of the AND circuits 50 and 54, drive the transistors 62 and 66.Further, when the standby signal ST or the signal Q* inverted from theoutput signal Q is held at an H-level, the signals, which are outputfrom the OR circuits 60 and 64 by the output of the AND circuits 52 and56, drive the transistors 62 and 66. By driving the transistors 62 and66, the transistor 62 outputs a motor UP signal and the transistor 66outputs a motor DOWN signal.

[0047] As shown in FIG. 2, the motor UP signal output from thetransistor 62 is input to a relay coil 68A of a relay 68 and the motorDOWN signal output from the transistor 66 is input to a relay coil 70Aof a relay 70.

[0048] The motor 14 is connected between a common terminal 68C of therelay 68 and a common terminal 70C of the relay 70. Further, contacts68B and 70B are respectively connected to the common terminals 68C and70C in a state in which the relays 68 and 70 operate and are connectedto a plus side terminal 72A of a battery 72 which supplies electricityfor driving the motor 14. Another contacts 68D and 70D are grounded inthe same way as a minus side terminal 72B of the battery 72.

[0049] In this way, as the relay coil 68A of the relay 68 is energizedby the motor UP signal output from the relay control circuit 40, thecommon terminal 68C is connected to the contact 68B and the motor 14 isdriven in the direction of raising the window glass 18. Further, as therelay coil 70A of the relay 70 is energized by the motor DOWN signaloutput from the relay control circuit 40, the common terminal 70C isconnected to the contact 70B and the motor 14 is driven in the directionof lowering the window glass 18.

[0050] Next, the operation of the present embodiment will be explained.

[0051] When the unillustrated ignition switch of the vehicle is turnedon and the power supply electricity Vcc is supplied as drivingelectricity, the power window system 10 can be driven. Moreover, thewatchdog circuit 34 outputs the reset signal RS by the supplying of thepower supply voltage Vcc. The microcomputer 30 is started by this resetsignal RS. When the starting of the microcomputer 30 begins, themicrocomputer 30 outputs the clock signal CK at predetermined cycles. Inthis way, the watchdog circuit 34 starts monitoring of the microcomputer30.

[0052] On the other hand, in the determination circuit 36, when theclock signal CK is input, the set signal S is output and the resetoutput signal Q is set and held at an H-level. The output signal Q isoutput to the AND circuit 38 as a signal for determining the operatingstate of the microcomputer 30 by the determination circuit 36. Namely,when the microcomputer 30 operates normally, a predetermineddetermination signal is output from the determination circuit 36.

[0053] The output signal Q from the determination circuit 36 and thestandby signal st from the microcomputer 30 are input to the AND circuit38. When the microcomputer 30 does not output the standby signal st, theAND circuit 38 outputs an L-level signal.

[0054] As shown in FIG. 5, when the standby signal ST is output, in therelay control circuit 40, the AND circuits 50 and 54 switch the outputsin accordance with the UP signal and the DOWN signal which are outputfrom the microcomputer 30 based on the operations of the UP switchSW_(U) and the DOWN switch SW_(D). In this way, the transistors 62 and66 are driven and the window glass 18 is raised and lowered.

[0055] As shown in FIG. 6(A), when the standby signal st is output fromthe microcomputer 30, the AND circuit 38 outputs the standby signal STin accordance with the standby signal st and the output signal Q of thedetermination circuit 36. This standby signal ST is input to thewatchdog circuit 34 and the relay control circuit 40.

[0056] Since the standby signal ST which is in accordance with thestandby signal st output from the microcomputer 30 is input to thewatchdog circuit 34, the watchdog circuit 34 enters the standby mode. Asa result, electricity to be consumed is cut down.

[0057] Further, as shown in FIG. 5, when the standby signal ST is inputto the relay control circuit 40, the outputs of the AND circuits 50 and54, in which the UP signal and the DOWN signal are input from themicrocomputer 30, are held at L-levels, and the transistors 62 and 66are driven on the basis of outputs of the AND circuits 52 and 56.

[0058] As shown in FIG. 6(A), when the watchdog circuit 34 enters thestandby mode, since the monitoring of the microcomputer 30 is suspended,the watchdog circuit 34 does not output the reset signal RS whichrestarts the microcomputer 30 to the microcomputer 30 even if the clocksignal CK is not input from the microcomputer 30. Moreover, when theoutput of the standby signal st is stopped, the standby mode of thewatchdog circuit 34 is terminated, and thereafter, the watchdog circuit34 resumes monitoring which is based on the clock signal CK output fromthe microcomputer 30.

[0059] On the other hand, as shown in FIG. 6(B), when the clock signalCK is not input from the microcomputer 30, the watchdog circuit 34outputs the reset signal RS to the microcomputer 30 and urges restartingof the microcomputer 30. The reset signal RS which is output from thiswatchdog circuit 34 is input to the determination circuit 36 as thereset signal R. When the reset signal R is input, the determinationcircuit 36 holds by switching the output signal Q to an L-level.

[0060] In this way, whether the standby signal st is input or not, theAND circuit 38 does not output the standby signal ST. Namely, as shownby a double-dashed chain line in FIG. 6(B), even if the standby signalst is input, since the clock signal CK is not input, the output signal Qis held in a reset state (at an L-level).

[0061] The reset output signal Q is also output to the relay controlcircuit 40. As shown in FIG. 5, when the reset output signal Q is inputto the relay control circuit 40, the transistors 62 and 66 are driven bythe outputs of the AND circuits 52 and 56 in the same way as the standbysignal ST is input.

[0062] In this way, in the microcomputer monitoring device 28, even ifthe standby signal st is input by mistake, the watchdog circuit 34outputs the reset signal RS for restarting the microcomputer 30 withoutentering the standby mode and can urge restarting of the microcomputer30. Moreover, since the relay control circuit 40 is switched so as todirectly control the motor 14 on the basis of the output signal Q of thedetermination circuit 36 which is input from the microcomputermonitoring device 28 and in accordance with the operation of the UPswitch SW_(U) and the DOWN switch SW_(D), an erroneous operation doesnot occur.

[0063] Further, when the standby signal st which is input by mistake isstopped, the microcomputer monitoring device 28 can start monitoring themicrocomputer 30 normally.

[0064] In a state in which the standby signal st is input to themicrocomputer monitoring device 28, the microcomputer 30 may berestarted due to the input of the power supply voltage Vcc or the like.FIGS. 6(C) and 6(D) show examples in which the microcomputer monitoringdevice 28 detects the standby signal st when the power supply Vcc isinput.

[0065] As the power supply voltage Vcc is applied, the watchdog circuit34 outputs the reset signal RS and urges starting of the microcomputer30. In this way, the output signal Q of the determination circuit 36 isreset. Thereafter, as shown in FIG. 6(C), even if the clock signal CK isinput from the microcomputer 30 to the determination circuit 36, sincethe set signal S is output to the FF circuit 48 due to the input of thestandby signal st, the output signal Q is held in a reset state.

[0066] Further, as shown in FIG. 6(D), the watchdog circuit 34 outputsthe reset signal RS and continuously outputs the reset signal RS unlessthe clock signal CK is input from the microcomputer 30.

[0067] On the other hand, as shown in FIGS. 6(C) and 6(D), because thereset output signal Q is input to the AND circuit 38, even if thestandby signal st is input thereto, the standby signal ST is not output.As a result, the watchdog circuit 34 does not enter the standby mode andcontinuously monitors the microcomputer 30.

[0068] In this way, for example, when the clock signal CK is stopped,the reset signal RS is output. Thereafter, when the clock signal CK isoutput from the started microcomputer 30, the microcomputer 30 stops theoutput of the reset signal RS and is continuously monitored.

[0069] Thus, in the microcomputer monitoring device 28 applied to thepresent embodiment, even if the standby signal st is input when themicrocomputer 30 is started, the microcomputer monitoring device 28 doesnot enter the standby mode and can continuously monitor themicrocomputer 30. Further, because the microcomputer monitoring device28 receives the standby signal st and enters the standby mode only whenthe microcomputer 30 operates normally, it can be prevented that, whenthe microcomputer 30 does not operate normally, the watchdog circuit 34enters the standby mode by the standby signal st which is input bymistake and that the microcomputer 30 cannot be monitored(restarted).

[0070] The above-described present embodiment shows an example to whichthe present invention is applied and the structure and the applicationof the present invention are not limited to the same. In the presentembodiment, an example is described of a case in which the power windowsystem 10 of the vehicle is provided at the vehicle operator's seat sidedoor 12. However, the present invention is not limited to this and maybe applied, in various types of control systems using a computer, to acomputer monitoring device in which a computer is monitored and stoppedbeing monitored on the basis of a first signal which is output from thecomputer in a predetermined cycle in accordance with a clock signal orthe like and a second signal which is output from the computer with apredetermined timing.

[0071] As described above, in the present invention, even if the secondsignal is input by mistake, start stopping means operates so as to notdisable the monitoring of the computer. As a result, a superior effectis achieved in that the computer can be reliably monitored even if thecomputer is started in a state in which the second signal is input.

1. A computer monitoring device, comprising: starting means whichoutputs a starting signal before starting a computer, said startingmeans outputting a starting signal to the computer when a first signal,which is output from the started computer in a predetermined cycle, isstopped for a predetermined period of time; start stopping means whichstops an operation of said starting means when a second signal, which isoutput from the computer with a predetermined timing, is input; startoperation determination means which outputs a third signal, which urgesstopping of an operation of said start stopping means, due to inputtingof the starting signal, said start operation determination meansstopping outputting of the third signal by the first signal which isoutput from the computer only when the second signal is not detected;and operation monitoring means which stops outputting of the inputsecond signal to said start stopping means when said start operationdetermination means outputs the third signal.